1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a means for inputting/outputting in parallel a data with plurality of bits.
2. Description of the Prior Art
Packages for semiconductor integrated circuit devices include many types such as dual in-line package (referred to as DIP hereinafter), small out-line package (referred to as SOP hereinafter), small out-line J-lead (referred to as SOJ hereinafter), quad flat package (referred to as QFP hereinafter), pin grid array, and the like. However, packages of the type having a line (series) of terminals on the mutually opposing pair of sides (edges) such as DIP, SOP and SOJ (generically referred to as DIP hereinafter) are generally in use.
Data or address signals which are input/output to/from a semiconductor integrated circuit device (referred to as an IC hereinafter) such as a memory device and a microprocessor are ordinarily bit parallel signals having a plurality of bits (for example, 4, 8, 16 bits or the like). On the other hand, in an IC of DIP type package, terminals for inputting/outputting these bit parallel signals are needed also for connection to a control signal source and a power supply, so it is not possible to accommodate these signals by only a line of terminals on one of the pair of sides. Therefore, it is general to constitute the terminals for these bit parallel signals by both lines of terminals on the pair of sides.
On the other hand, on a semiconductor chip which is sealed in the interior of the package, there are formed pads in the vicinity of each terminal of the line of terminals along two sides that correspond respectively to the above-mentioned pair of sides, where these pads are respectively connected to the corresponding terminals by means of bonding wires.
When the above-mentioned semiconductor chip is a memory chip, there are formed on the surface of the chip a memory cell array part which carries out data read/write at a designated address in response to the bit parallel signal that is input/output through the plurality of terminals and pads, and a selection and data transfer control part which carries out the transfer of a bit parallel data to this designated address.
Similarly, when the above-mentioned semiconductor chip is a microprocessor, there are formed on the chip surface a data processing circuit which includes a data holding part which holds temporarily a bit parallel data itself that is input/output through the plurality of terminals and pads, an intermediate processed result and the final processed result of the data, and a data processing part which receives a data from the data holding part and returns it to the data holding part after applying a predetermined processing to the data, and a selection and data transfer control part which carries out data transfer control among the plurality of pads, the data holding part and the data processing part in response to the type of the data and the contents of the processing.
Since it is advantageous to arrange and form each of these circuits formed on the surface of the semiconductor chip collected as a block for each function, the memory cell array part, the data processing circuit, the selection and data transfer control part or the like are arranged and formed on the semiconductor chip as respective independent blocks without subdivision unless specifically needed to do so.
Namely, for the case memory chip, a plurality of pads are formed along the pair of sides, and the memory cell array part and the selection and data transfer control part are formed respectively in the region between the pair of lines of pads.
Similarly, for the case of microprocessor, the data processing circuit and the selection and data transfer control part are arranged and formed along the pair of sides in the region between the pair of lines of pads.
In the region on the semiconductor chip where the selection and data transfer control part is formed there are formed a plurality of data buses for performing data transfer in bit parallel fashion between the pair of lines of pads and the designated address, between the pair of lines of pads and the data holding part and the data holding part and the data processing part, and these data buses are connected respectively to the pads of the pair of lines of pads.
The selection and data transfer control part and the data buses formed in the above-mentioned manner on the semiconductor chip are necessarily deviated to one of the two lines of pads on the chip. Therefore, the wirings between the plurality of pads of one line of pads and the data bus become shorter than the wirings between the plurality of pads of the other line of pads and the data bus. Accordingly, the transmission time of either one of the data becomes longer due to the difference between the resistances and the wiring capacities of these wirings. Since the transmission time of a bit parallel signal is determined by the transmission time of a bit which requires the longest time of transmission among a plurality of parallel bits that constitute the signal, the data transfer time for the IC as a whole becomes long and its operating speed is reduced.